System-on-chip (SOC) integrated circuits are becoming ever more popular in various applications including embedded applications such as with set-top-boxes, mobile phones, portable media devices, and so on. Especially with portable SOC applications, power management functionality may be a desired aspect of many SOC implementations. One way to reduce power consumption is to control the clocks provided to peripherals in an SOC by slowing them down or turning them off dynamically when feasible.
FIG. 1 shows a typical power management implementation in an SOC. The depicted SOC portion has a core 101, clock control logic 102, power management logic 104, and peripherals 106 (e.g., graphics controller, universal serial bus client, universal asynchronous receiver/transmitter, and the like). The power management logic 104 typically has a timer to monitor system events indicating the state of a peripheral. When events indicate that a peripheral has a lack of activity for a period of time, the power management logic sends a request to the peripheral to enter it into a power saving state. The peripheral then responds by sending an acknowledge signal. This handshaking is typically necessary to avoid uncompleted, pending transfers or tasks (e.g., pending FIFO or bus transfers). When the power management logic receives the acknowledge signal, indicating that the peripheral is ready to go into a power reduction state, it gates off or slows down the clock provided to the peripheral. This is typically implemented via the clock control logic 102. Unfortunately, such schemes may have some drawbacks and thus, a new approach may be desired.